MMA5248WR2【PDF 34/58 页】IC ACCELER 480G X-AXIS 16QFN

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4.2.1.1

Synchronization Pulse Detection

The Synchronization (Sync) pulse detection block generates a valid synchronization pulse signal following the detection of an

externally generated Sync pulse. This signal resets the Sync pulse time reference (t TRIG ), and initiates the timers associated with

response messages.

The supply voltage can vary throughout the specified range, so the external Sync pulses may have different absolute voltage

levels. Thus, the Sync pulse detection threshold (V CC_SYNC ) is dependent not only on the Sync pulse absolute voltage, but also

on the supply voltage. Figure 27 shows a block diagram of the Sync pulse detection circuit.

V CC

SYNC_OFF

SYNC_OFFSET

V SYNC_REF

SYNC_LPF

V SYNC_COMP

f OSC /2

COUNTER

CONTROL

LOGIC

SYNC_DET

SYNC_LPF_RESE T

SYNC_LPF_RESET

V SS

Figure 27. Synchronization Pulse Detection Circuit

The start of a Sync pulse is detected when the comparator output is set (V SYNC exceeds V SYNC_REF ). The comparator output

is input into a counter, and the counter is updated at a fixed frequency of f OSC /2. At a fixed time after the initial sync pulse detection

(t SYNC_LPF_RST_ST ), the counter is compared against a limit (the minimum value of t SYNC ). If the counter is above the limit, a valid

sync pulse is detected.

If the Sync pulse is valid, the following occur:

1. The valid Sync pulse detection signal is set.

2. The detection counter is reset and disabled for t SYNC_OFF (referenced from t TRIG ). t SYNC_OFF is a user

programmable option. Reference Section 3.1.3.6 for details on the selectable option, and Section 2.6 for timing

specifications for each option.

a. If BLANKTIME = ‘0’, t SYNC_OFF = t SYNC_OFF_500

b. If BLANKTIME = ‘1’, t SYNC_OFF =t SYNC_OFF_VAR = t TIMESLOT_DLYx + (2+DATASIZE+(P_CRC?3:1)) *t BIT_x

3. The Sync pulse detection low-pass filter is reset for a specified time (t SYNC_LPF_RESET).

If the Sync pulse is invalid, all timers are reset, and the detector becomes sensitive for the very next f SYNC_DET sample.

The output of the comparator is monitored at the f OSC /2 frequency. Once the comparator output goes high, all of the internal

timers are started, so that the t TRIG jitter is minimized.

MMA52xxKW

Sensors

Freescale Semiconductor, Inc.

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